ASIC Design Flow Using Simulink and Cadence Digital IC Design Tools

The complexity of modern ASICs has increased the demand for efficient methodologies that integrate the implementation of high-level modeling with the back-end physical layout design. This integration enables the implementation of complex algorithms as systems on chip (SoC). In this work, a continuousstate model is first discretized by the designer and then digitized by the Simulink HDL coder to extract a synthesizable RTL code along with a testbench. The RTL code is simulated with the test bench in Cadence Xcelium to verify the logic and functionality of the design. This logic is then synthesized in the Genus Stylus UI mode. The gate-level netlist produced as a result of this synthesis is used for digital IC design using 45 nm technology library files. This synthesized design database is then processed for physical design implementation to obtain the DRC and LVS-clean chip layout. This work demonstrates the complete design flow, from frontend definition and simulation in Simulink to layout design and verification in Cadence tools. Although based on a simple 3-bit SISO register, the proposed methodology demonstrates an efficient, scalable approach for ASIC implementation, achieving a $39.4 \%$ total power reduction through clock gating, and a DRC/LVS-clean layout using a unified Simulink-Cadence toolchain.