BAM-Net: Hardware Friendly Associative Memory Using Binary Dominant Weights and NAND Logic

This paper presents BAM-Net, a hardware-efficient binarization algorithm designed for associative memory (AM) implementation. BAM-Net aims to reduce memory overhead, power consumption, and implementation complexity. Motivated by the observation that the largest positive weight in each row of a Hebbian-trained weight matrix dominates the recall process, the proposed approach retains only this maximum weight per row. This yields a highly sparse binary matrix containing only 0 and +1 values. The resulting simplification enables the exclusive use of standard NAND gates in hardware implementation, thereby eliminating the need for multi-level weight storage or complex arithmetic operations. Experimental results on synthetic $7\times 5$ pattern recall and the binarized MNIST dataset demonstrate that BAM-Net achieves superior recall accuracy, up to 96.2% and 92.7% respectively, while reducing memory usage by over 50% compared to state-of-the-art quantum, photonic, and quantized AM models. The proposed method converges in fewer recall attempts and exhibits excellent scalability, making it well suited for low-power, real-time, and resource-constrained hardware applications.