Robust HV JFET With Split-PBL and Resistive Field Plate for Flexible VP Design and Enhanced Current Capability

This article proposes a split P-type buried layer (SPBL) method together with resistive field plate (RFP) technology for high-voltage junction FET (JFET) design to address the optimum design difficulty among flexible pinch-off voltage (V_P), sufficient OFF-state breakdown voltage (BV_DS), and saturation current (I_SAT). The RFP and SPBL function as a reduced surface field (RESURF) layer, redistributing the surface electric field to improve BV_DS. Meanwhile, the original PBL can be designed to achieve flexible V_P by setting the relative position between the top and bottom gate, which can be precisely adjusted by the implant mask without affecting the RESURF. Implemented on a 0.35 ${\boldsymbol}{\mu}$m Bipolar, CMOS, DMOS (BCD) platform, the high-voltage (HV)-JFET achieves a BV_DS of 830 V and V_P ranging from -12 to -35 V, with a limited drain-induced barrier lowering (DIBL) effect of 4 V across a 0.1–100 V drain voltage range. Current capability reaches 115 ${\boldsymbol}{\mu}$A/${\boldsymbol}{\mu}$m, which is comparable to triple-RESURF technology. Key design parameters such as SPBL position, curvature radius, and drift length are discussed as well. Moreover, BV_DS shifting is analyzed through TCAD simulations and high temperature reverse bias (HTRB) on-wafer testing. Preliminary wafer results reveal an electron-trapping suppression mechanism, leading to BV_DS shifting. After process optimization, the HV JFET with SPBL and RFP technology demonstrates robustness in the HTRB testing.