A Time-Domain Integration Comparison Scheme With Noise Immunity for Wake-Up Receivers

Traditional wake-up receiver (WuRX) systems based on voltage-domain comparators for weak signal detection can readily suffer from false triggering due to noise. To address this issue, this work analyzes the mechanism of noise-induced failure in traditional voltage-domain comparator and proposes a time-domain comparator (TDCMP) scheme based on time-domain integration. By temporally integrating the input signal, the noise immunity of the comparator is significantly enhanced. To suppress process, supply voltage, and temperature (PVT) drift in the TDCMP, this work designs a frequency-locked loop (FLL) that employs a voltage-controlled oscillator (VCO) isomorphic to the TDCMP’s voltage-controlled delay line (VCDL) for drift calibration while simultaneously providing the clock signal for the WuRX. Implemented in a 65-nm CMOS process, the core chip area is 0.23 mm², with a total system power consumption of 20.9 nW. The measurement results demonstrate that the proposed TDCMP enhances the WuRX sensitivity by 4 dB.