Optimizing Monolithic CFET Middle-of-Line Contact Architectures at A10 Node: A DTCO Simulation Study

As transistor scaling approaches physical limits, monolithic complementary field-effect transistors (CFETs) offer a promising path forward but suffer from critical parasitic challenges in middle-of-line (MOL) interconnects. We propose a semi-wrap-around contact (Semi-WAC) scheme that simultaneously mitigates parasitic resistance and enables cell height scaling. Here, we systematically optimize MOL contact architectures through design-technology co-optimization (DTCO), evaluating top contact (TC), wrap-around contact (WAC), and Semi-WAC schemes with single-, dual-, and triple-nanosheet stacks, respectively. Through 3-D TCAD and SPICE simulations, Semi-WAC significantly reduces parasitic resistance at three-stacked nanosheet CFETs (N_NS=3), increasing ON-current 9.1%. By further integrating gate spacer dielectric constant (k = 3.0) to suppress parasitic capacitance, Semi-WAC resolves the inherent RC tradeoff of wraparound contacts, achieving 8.5% higher maximum frequency f_max and 11.3% lower dynamic power. This demonstrates Semi-WAC with low-k spacer optimization as a scalable solution for next-generation CFETs.