Across-Array LDPC Codes Design for Resistive Random-Access Memories

Resistive Random-Access Memory (ReRAM) has garnered significant attention due to its high storage density, rapid read/write speeds, and compatibility with CMOS devices. However, the simple crossbar structure of ReRAM introduces sneak path (SP) interference, which impairs the storage reliability of the ReRAM system. To address this, we propose a novel Zoned Namespace (ZNS)-based ReRAM storage scheme, which is well-suited for scenarios with hybrid storage protection of multi-type data and employs low-density parity-check (LDPC) codes to mitigate the impact of sneak paths. Furthermore, considering the asymmetric nature of the ReRAM channel, we first develop a computer-calculable Asymmetric Discrete Density Evolution method for the belief propagation decoding algorithm (ADDE-BP). Due to the across-array storage structure, sneak path interference and noise vary across sub-arrays, resulting in codewords experiencing a non-uniform “sum channel”. To address this, we further propose criteria based on ADDE-BP for non-uniform error correction, specifically for the design of low-density parity-check (LDPC) codewords. Simulation results show that the proposed codes achieve 1–2 orders of magnitude lower BER than IEEE standard codes and Mackay codes under most channel conditions, thus demonstrating that our proposed LDPC code design for across-array applications enhances data storage reliability compared to conventional methods. Most importantly, the maximum check node degree and node type of the designed code were reduced, thus greatly simplifying the hardware implementation. This work establishes a co-design framework for ReRAM that simultaneously improves the reliability and efficiency of storage systems.