Single Event Transient Characterization of a Low-Dropout Regulator in a sub-20 nm CMOS Technology

In this paper, the mechanism of SET (single event transient) of a LDO (low-dropout regulator) fabricated in a sub-20 nm FinFET (fin-field effect transistor) technology were studied. SPICE (simulation program with integrated circuit emphasis) circuit simulation finds that the most sensitive nodes are inside the EA (error amplifier) and BGR (band gap reference). Moreover, the mechanism of generating SET was also studied. Furthermore, the SET characteristics of the LDO test chip were further studied through heavy ion experiments. The result of the SET width and amplitude statistical distribution found in the experiment is consistent with the SPICE circuit simulation result by histogram analysis, confidence interval and hypothesis testing, which confirms the conclusion of the SPICE circuit simulation through a view of statistics. Based on the above analysis results, a radiation-hardened LDO was also proposed based on a comparator and pump transistor focusing on the output of EA. In positive SET pulse situation, the pulse width before and after the reinforcement is 55.83% shorter. The pulse amplitude is reduced by 91.37% through SPICE circuit simulation; in negative SET pulse situation, the pulse width before and after the reinforcement is 35.25% shorter, and the pulse amplitude is reduced by 78.30%, in BGR output situation, the pulse width before and after the reinforcement is 55.83% shorter, and the pulse amplitude is reduced by 91.37%; finally, through the analysis of power consumption and area calculation before and after hardening, the effectiveness of the hardening design was verified.