An Interface ASIC for MEMS Disk Resonator Gyroscope With 0.018°/h Bias Instability and 108 ppm Scale Factor Nonlinearity

This paper presents a monolithic interface application-specific integrated circuit (ASIC) for a MEMS disk resonator gyroscope (DRG) with low zero-rate output (ZRO) drift and low scale factor (SF) nonlinearity. The ASIC is implemented under a high-precision force-to-balanced (FTR) mode combined with an easily integrable self-excitation drive loop. The ASIC improves the performance in two ways: First, based on an analysis of electrical errors in MEMS DRG performance, a time-domain anti-coupling architecture is proposed to reduce electrical coupling effects on ZRO drift and SF nonlinearity. This architecture also eliminates the need for high-bandwidth signal processing compared to traditional frequency-domain architectures. Second, the first-order linear relationship between ZRO drift and drive amplitude voltage in the FTR mode is analyzed and validated, and a low hardware compensation circuit is designed to correct ZRO drift. The ASIC is fabricated using a $0.35\mu $ m BCD process with a chip area of 4.3 mm $\times 4.2$ mm. Combined with the MEMS structure, it achieves a bias instability (BI), angle random walk (ARW), and SF nonlinearity of 0.018°/h, 0.0055° h, and 108 ppm, respectively.