D-Band, 2-D Scalable CMOS Planar Phased Array Transmitters With λ/2-Spaced Integrated Antenna

To exploit the >100-GHz spectrum and overcome the attenuation of the wireless channel, a large-scale CMOS phased array is indispensable. However, the size of the array is currently limited by the loss and imbalance of the classic binary distribution network. In addition, since the available chip area shrinks quadratically with the wavelength ( $\varpropto \lambda ^{2}$ ), a >100-GHz $\lambda $ /2-spaced planar array is highly challenging. To solve the above issues, this article presents a D-band, 2-D scalable CMOS planar phased array transmitter (TX) with a precise $\lambda $ /2 antenna spacing. It employs a traveling-wave LO/IF distribution network, which enables the 2-D scalability by cascading the CMOS TX chips through the chip-edge wire bonding. Inside each chip, four highly integrated TXs perform the IF amplitude and phase control, and the IF-to-RF upconversion. The LO amplitude attenuation is compensated by a proposed subsampling (SS) tripler. Furthermore, a triple-resonance, on-chip antenna feed with quartz superstrate achieves a 3-dB bandwidth of 16 GHz (12%) and a 42% area reduction. Then, the $134\sim 141$ GHz, 16- and 64-element CMOS planar phased arrays are built. In the measurement, a peak effective isotropic radiated power (EIRP) of 26 dBm and an output RF power of 20 mW are recorded at 138 GHz for the 16-element array. In both the vertical and horizontal directions, a ±40° beam steering angles are recorded. The 64-element phased array exhibits a 35-dBm EIRP and a ±60° beam steering capability. A 10-m light-of-the-sight (LoS) transmission of a 14 Gbit/s, 16-quadrature amplitude modulation (QAM) data stream with an error vector magnitude (EVM) of 9.8% is also demonstrated.