Chip-Level Interconnection Techniques for Chip Embedding Integration of SiC MOSFETs

Chip embedding is emerging as a promising advanced packaging technology, offering significant advantages over conventional methods in performance, reliability and miniaturization. This work focuses on the topside and backside die-level interconnection techniques needed for enabling chip-embedding implementation. A novel in-house technique is presented to selectively re-metallize with Cu the contact pads of any device by hard shadow masking, to allow subsequent micro-via standard PCB contact process. In this work the technique is used to re-metallize the gate and source pads of 750V-12mΩSiC MOSFET dies, which are then attached to Cu leadframes with a robust Ag sinter paste. These assemblies have been successfully embedded for implementing elementary switching- cells used in multilevel power converters designed for electric traction applications.