A Study on a 4H-SiC-Based ESD Protection Device with Lower Operating Voltage Using an Additional PNP BJT Structure

This paper proposes a 4H-SiC-based ESD protection circuit that improves trigger voltage characteristics while maintaining low on-resistance and uniform turn-on behavior by adding a PNP structure to the Gate-Grounded NMOS (GGNMOS). To address the issue of high operating voltage in conventional 4H-SiC-based GGNMOS, the proposed design incorporates an additional PNP BJT and a P+ implant region into the existing GGNMOS structure. The electrical characteristics of the proposed circuit were evaluated and compared to the conventional structure using Transmission Line Pulse (TLP) testing. The optimization of trigger voltage and snapback characteristics was also verified based on design parameters. The proposed structure provides an improved design window and shows the potential for reliable ESD protection in low-voltage applications. This research represents a significant step forward in 4H-SiC-based ESD protection circuit design and is expected to be applicable to various environments.