Engineering Extrinsic Resistance of E-Mode GaN p-FET Towards Enhanced Current Density

E-mode GaN p-FETs with high maximum drain current density $\left(I_{\max }\right)$ are an essential component for GaN complementary logic (CL) circuitry and power integrated circuits (PICs). However, the current density of such devices often fails to meet expectations. In this work, we identified a crucial mechanism that limits the $I_{\max}$ of GaN p-FET: the large access region resistance $(R_{\mathbf{a}\mathbf{c}\mathbf{c}})$ which reduces the effective gate-to-channel voltage. A new GaN p-FET structure is proposed, featuring an Al0.7 Ga0.3 N (~3.5 nm) insertion layer (ISL) at the access region. The polarization effect of the Al0.7 Ga0.3 N enhances the ionization of Mg acceptors, and $R_{\mathbf{a}\mathbf{c}\mathbf{c}}$ is reduced. The lowered $R_{\mathbf{a}\mathbf{c}\mathbf{c}}$ results in a higher effective gate bias $(V_{\mathrm{G}\mathrm{S}-\mathrm{e}\mathrm{f}\mathrm{f}}= \left.V_{\mathbf{G}\mathbf{S}}-I_{\mathbf{D}} \cdot R_{\mathbf{S}}\right)$ and increases $I_{\max }$ , The fabricated p-FET with $L_{\mathbf{G}} =2 \mu \mathrm{m}$ achieves E-mode operation with a $V_{\mathrm{t}\mathrm{h}}=-3.5 \mathrm{V}$ and a high $I_{\mathbf{O}\mathbf{N}}/I_{\mathbf{O}\mathbf{F}\mathbf{F}}$ ratio of $10^{7}$ , The new p-FET structure exhibits a larger $I_{\max}$ of 17.5 $m$ A/mm compared to 5.6 $m$ A/mm for the conventional p-FET. These results validate the prospect of the proposed p-FET for the integration of GaN-based CL circuitry and PICs.