Improving Error Correction with Weak-Bit Information in Resistive Memories

This paper presents a way to improve the error correction capability of binary block error-correcting codes used in resistive memories. The proposed solution relies on a better exploitation of the bits suspected of being erroneously sensed. Once identified in a sensed memory word, such weak bits are flipped and error decoding is resumed with better chances of success. This works with an error-only decoder unable to handle any kind of soft information by itself. It is shown that the uncorrectable bit error rate can be reduced by up to an additional order of magnitude if the weak-bit information is leveraged not only in the presence of detectable uncorrectable errors but also in the case of certain conventionally undetectable errors. The same applies to the uncorrectable and undetectable bit error rate. These improvements can be achieved with limited latency and logic overhead, and without storage overhead.