Engineering Ferroelectric Gate Dielectric to Achieve High-Performance Multilevel Organic Transistor Nonvolatile Memories With the Programming/Erasing Voltages Below 10 V

It is urgent to overcome the bottleneck problems of high programming/erasing (P/E) voltage and slow P/E speed in the multilevel thin-film transistor nonvolatile memories (NVMs), for promoting their development to meet practical applications. In this letter, we propose an efficient strategy to resolve the both bottlenecks, by engineering the ferroelectric gate dielectric in organic thin-film transistors (OTFTs). As a result, our OTFTs exhibit excellent four-level NVM performances, with highly reliable endurance over 1000 cycles and highly stable retention over 10000 s, at the very low P/E voltages of ±10 V and a short pulse of 2 ms. The relevant mechanisms are investigated in detail. This work paves the way toward the development of next-generation fast-speed, high-capacity NVM.