A Review of Engineering Techniques for CMOS On-Chip Inductor Design and Quality Factor Enhancement From MHz-to-GHz Frequency Domains

This paper presents a comprehensive review of engineering techniques employed to enhance the quality factor (Q-factor) of silicon-based on-chip inductors across MHz-to-GHz frequency domains. The performance of CMOS on-chip inductors is often bottlenecked by the substrate losses, parasitic effects and resistive losses, which degrade the Q-factor. Numerous engineering techniques including substrate engineering, ground plane engineering, layout engineering and material engineering are analyzed and discussed. Substrate engineering such as substrate isolation and micromachining, ground plane engineering such as patterned ground shield and defected ground shield, layout engineering such as multilayer stacking and geometry modulation, material engineering such as magnetic core integration and conductor lamination are all investigated. A comparative evaluation of these techniques highlights the optimum approaches for attaining high-Q inductors in silicon process, mainly for CMOS compatibility.