Mitigating Threshold Voltage and Current Sharing Mismatch in Paralleled SiC MOSFETs Using Optimized Passive RC Delays

In high-performance applications like aerospace and industrial operations, H-bridge derived converters using silicon carbide (SiC) MOSFETs face challenges from threshold voltage (V_TH) and current-sharing mismatches between parallel devices. These mismatches lead to uneven current distribution, increased thermal stress, and reduced efficiency. This paper proposes a solution to mitigate transient current-sharing mismatch in parallel SiC MOSFETs within a modular non-inverting buck-boost (NIBB) converter. A multi-variable analytical model is developed to describe the time-dependent gate-to-source voltage (V_GS) dynamics, considering V_TH mismatches and parasitic effects. Based on this model, an optimized RC filter network connected to both turn-on and turn-off paths is designed to synchronize switching behavior across devices with differing threshold voltages. The method is validated through LTspice simulations, which show a 42% reduction in transient current mismatch, and experimentally on a 200W all-SiC 100kHz NIBB converter, where an 18.6% reduction in peak current imbalance is achieved. Furthermore, the method improves efficiency by 1.6%, mainly by reducing turn-on and turn-off losses. This study demonstrates the effectiveness of RC-filter-based gate drive optimization in enhancing reliability and efficiency in SiC power converters.