Design And Validation Of Low Power Low Area High Speed Mixed Logic 4 Bit Comparator

This research work proposes an N-bit low-power, high-speed comparator with an emphasis on area efficiency. The digital comparator designed here is to minimize power and hardware usage, thus making it a more efficient option. Comparison is one of the basic mathematical operations; however, conventional comparator designs are plagued by high schematic complexity, more power consumption, and increased delays. Our suggested approach overcomes these challenges using a parallel prefix tree structure, which allows bit-by-bit comparison from the most significant bit towards the least significant bit without unnecessary comparisons when bits are the same. The comparator design includes two main modules: an OR gate realized using domino logic and an AND gate realized using transmission gates. The design was realized with Virtuoso 45GPDK CMOS technology at 1 GHz frequency, and simulations were performed using Spectre. Experimental results show a 70.76% decrease in power consumption and a 31.92% increase in operating speed over current comparator models, emphasizing the performance and efficiency benefits of our method.