Enhancing SRAM Efficiency and Stability with Self Pull Up Mechanism and Bitline Charge Sharing

Modern electronic systems rely heavily on SRAM (Static Random Access Memory) because of its low latency and rapid speed. However, as technology scales down and energy-efficient applications become increasingly critical, traditional SRAM designs struggle to balance power consumption, stability, and performance. Addressing these challenges is essential for emerging battery-powered and energy-sensitive devices, where near-threshold V^th operation is highly desirable to reduce power usage. This paper proposes a novel SRAM architecture combining a Self-Pull-Up Mechanism (SPUM) with Bitline Charge Sharing (BCS) to enhance energy efficiency and performance under near-V^th conditions. The SPUM dynamically adjusts pull-up strength to improve read stability, while the BCS technique minimizes bitline voltage swings, effectively reducing dynamic power consumption and delay overhead. Additionally, the Write Failure Sensing Circuit (WFSC) ensures reliable write operations by incorporating a two-phase methodology: supply voltage collapse during the write process and dynamic charge sharing to assist high-σ cells. Simulation results validate the proposed design, demonstrating an average power consumption of 29.82 nW, a peak power of 29.99μWat t=4.0001*10^-5s, and a minimum power of 2.48 nW at t=1.26284*10^-5s. with no observable failures, achieving significant reductions in both static and dynamic power consumption while maintaining stability and write-ability. These results highlight the potential of the SPUM-BCS integration to set new benchmarks for low-power SRAM architectures, making it a superior choice for next-generation energy-sensitive applications.