Area-Efficient Realization of Three-Input Logic Functions Using Hybrid SET-MOS Transistors

Logic synthesis is a crucial step in the electronic design automation (EDA). While two-input logic gates can be easily implemented with MOS transistors, realization of multiple-input (or three-input, in particular) functions remains to be less area-efficient at transistor level. This paper presents an area-efficient realization for any three-input logic functions by using single-electron transistors (SETs) combined with MOS transistors. Results show that with their unique oscillation characteristics, SETs can provide significant improvement for logic synthesis in terms of transistor count over pure CMOS counterparts. This could potentially change traditional design paradigms in the EDA.