TableCache: An Open-Source, Configurable, Last-Level Cache for FPGA Systems

The performance of FPGA systems is increasingly limited by the latency and bandwidth of off-chip memory. The traditional ASIC solution of using caches has also been both studied and implemented on FPGAs. However, such works have largely focused on primary caches, and fail to optimize for the unique resources modern FPGAs offer like LUTRAMs. Additionally, many recent developments in ASIC caching (e.g. new cache replacement policies and victim caches) have not been evaluated on FPGA systems, which provide less opportunity for improvement because of lower cache miss latencies. This work presents TableCache: an open-source, configurable, last-level cache for FPGA systems that makes prolific use of LUTRAM-based structures. This allows our design to use 51% fewer LUTs than a directly-comparable commercial FPGA lastlevel cache while offering lower read-hit latency and running on average at 29% higher frequencies. The parameterization of TableCache also allows us to explore different cache replacement policies, where we find that Static Re-Reference Interval Prediction (SRRIP) can reduce average memory access time by 6.4% compared to Least Recently Used (LRU) while using fewer FPGA resources. We also find that the impact of last-level victim caching on FPGAs is largely negative, with a marginal 0.21% reduction in average memory access time (measured in cycles) significantly outweighed by a 32.4% increase to cache LUTs and a 16.9% reduction in operating frequency.