Sensing Timing Margin Contingencies in the Programmable Fabric of FPGAs

Vendors design the Programmable Logic Fabric (PL) of an FPGA for robustness over a wide range of customer designs, use cases, and operating scenarios. These specifications cover for Process-Voltage-Temperature (PVT) variations occurring on the PL and are meant to ensure reliable timing margins on the FPGA. With increasing power densities, advanced packaging techniques and the use of PL for data-intensive computations, there have been efforts to understand the effects of voltage transients on the PL and their dependence on workloads. In this work, we propose a scalable methodology based on soft digital sensor (SDS) to characterize on-die voltage transients for compute-intensive workloads. This method is scalable with respect to test, measurement, and debugging compared to prior work. In addition, we show how the proposed methodology can be extended to study trends of timing margins and voltagefrequency headroom on FPGAs. This can improve the energy efficiency of designs running at a fixed operating point or using dynamic voltage-frequency scaling. Our results gathered from an AMD Versal VCK190 FPGA board running multiple highactivity workloads show incidents of large voltage droops of nearly 100 mV using the SDS. We also observe between 18-31% frequency headroom available across the higher activity designs analyzed in the presence of droop and jitter. These margins potentially allow designers to reliably push the operating voltage and frequency beyond the limits specified by the FPGA vendors, leading to much improved energy efficiencies.