A Compact D-Band Stacked Power Amplifier With 16.1-dBm P sat and 636-mW/mm2 Power Density

This letter presents a D-band power amplifier (PA) fabricated in 40-nm bulk CMOS technology. The proposed design employs a T-model analysis of the internal node between the common-source (CS) and common-gate (CG) transistors in the stacked-FET structure. Based on this analysis, an optimized T-network was implemented to mitigate phase misalignment, resulting in boosted output power and power-added efficiency (PAE). Measurement results demonstrate a saturated output power ( $P_{\mathrm {sat}}$ ) of 16.1 dBm, peak PAE of 12.5%, and a gain of 32.2 dB, achieving the highest reported power density of 636 mW/mm² among CMOS-based D-band PAs. It further supports 16-/64-QAM data rates of 16 and 12 Gb/s, respectively.