A Reduced Switch Series Topology 15-level and 27level Multilevel Inverter

In the fast-evolving technological advancements in the power conversion from DC to AC, multilevel inverters play a pivotal role in obtaining signals with less harmonic distortion. Reduced switch topologies of multilevel inverters are known for their flexibility in synthesizing several levels of voltages with less no. of switches, sources and diodes which greatly reduces the size of the device. This paper investigates the performance of nearest level control pulse width modulation (PWM) based series topology of Asymmetrical 15-level and 27-level Multilevel Inverter with R, RL load. The total harmonic distortion (THD) of the voltages and currents of R, RL load was found to be under the IEEE 519-2022 standards. The proposed model has been simulated in the MATLAB/Simulink simulation environment and the results have been analysed using the FFT analyser of the MATLAB.