A Sampling-Based Warm-Up Distance Allocation Method Based on Reuse Distance Vectors

Effective warm-up of processor state is crucial in sampled simulation to ensure accuracy without incurring excessive simulation time. Traditional sampled simulation often uses a fixed (equal-length) warm-up for all sampling points, neglecting the varying locality and cache behavior of different code segments. We propose Reuse Distance Vector (RDV) to adaptively allocate warm-up lengths by quantifying segment-level sensitivity. First, we collect a reuse distance vector for each code segment, capturing the temporal locality of memory references. We then vary the warm-up length for training segments and measure L1-D cache miss-rate error relative to a fully warmed baseline, fitting a linear model to quantify each segment's sensitivity (the warm-up-error slope). A backpropagation-trained neural network takes the RDV as input and predicts this slope. The predicted slopes and segment weights (e.g. instruction counts) are used to allocate a total warm-up budget across segments. Finally, a truncation mechanism caps excessively long allocations to avoid diminishing returns. Our method reduces the required total warm-up while maintaining accuracy. In experiments with SPEC CPU2006 on the Gem5 simulator (using both AtomicSimpleCPU and DerivO3CPU models), the RDVbased allocation significantly lowers the sampling error in L1D cache miss rate compared to equal-length warm-up, and demonstrates superior performance over the Memory Reference Reuse Latency(MRRL) method in scenarios with diverse memory access patterns. The reuse distance vector inputs and the trained neural model are shown to be reusable across similar workloads, making this approach broadly applicable for accelerating sampled microarchitecture simulation.