FPGA Implementation of a Hardware-Optimized Autonomous Real-Time Radar Altimeter Processor for Interplanetary Landing Missions

This paper presents the design and development of a hardware-optimized, autonomous, real-time, flexible, and programmable onboard Radar Altimeter Processor (RAP) based on a Field Programmable Gate Array (FPGA) for autonomous interplanetary landing missions. Precise altitude detection across a wide range, from kilometers to touchdown, requires accurate beat frequency detection with a sufficient received signal-to-noise ratio (SNR). The processor integrates signal processing techniques, employing floating-point computation strategically to enhance altitude measurement precision and ensure concurrent data processing for real-time output. Additionally, the design incorporates rigorous Software Quality Assurance (SQA) checks and radiation-hardened components to ensure reliability in the challenging radiation environment of space. The efficacy of the optimized RAP implementation was validated through extensive laboratory simulations, FPGA prototyping, field tests, and Hardware-In-Loop Simulations (HILS) across diverse interplanetary landing scenarios. Notably, the RAP demonstrated exceptional performance during the autonomous landing of the Vikram Lander on the Chandrayaan-3 mission by ISRO/India. This processor presents a promising solution for future interplanetary missions, facilitating accurate and safe landing operations on celestial bodies with varying terrain and environmental conditions.