A 2.9-Gb/s Spread-Spectrum Clocking Transceiver Using Phase Interpolation for Chip-to-Chip Links

By lowering peak emissions, the spread-spectrum clocking (SSC) helps meet regulatory standards for EMI, which are critical in systems with high-speed interconnects. This paper demonstrates a fully integrated 2.9-Gb/s SSC transceiver at 45.8 kHz modulation frequency and -1.5% modulation depth. The PLL generates 2.9-GHz 4-phase clocks for the transmitter to generate the SSC clock to drive data, and 725-MHz 4-phase clocks for the receiver to recover the clock through the timing recovery loop. The phase-interpolating technique is employed for the SSC generation of the transmitter and for the clock recovery of the receiver. Implemented in 90-nm CMOS process, the transceiver consumes 53 mW and the EMI attenuation is more than 24 dB.