An 88-Gb/s/pin Single-Ended PAM-4 Transmitter in 28-nm CMOS With Duty-Cycle-Error and Quadrature-Phase-Error Correction Using Pre-Coded Data Patterns

This paper presents an 88-Gb/s/pin pseudo open drain (POD) four-level pulse amplitude modulation (PAM-4) single-ended voltage-mode transmitter (TX) with duty-cycleerror and quadrature-phase-error correction using pre-coded data patterns for the high-speed dynamic random access memory (DRAM) interface application. The proposed TX employs a newly proposed phase and duty-cycle error correction technique using pre-coded data patterns, which corrects errors caused not only by clock distribution but also by data path mismatches. The TX achieves $>44 \text{mV}$ eye opening, ${>}$ 0.15 UI eye width, $>0.96$ ratio of level mismatch (RLM) with 1.51 pJ/b at 88-Gb/s PAM-4 signaling for the 2³¹-1 pseudo random binary sequence (PRBS-31) pattern.