Genesis: A High Speed Methodology for Gate Level Netlist Extraction from Spices

Due to the demand for high-performance chips and high design costs, original equipment manufacturers follow a lateral approach and send physical layouts (GDSII) to third-party entities. It is challenging and time-consuming to reverse engineer the physical layout to extract the gate-level netlist because of the complexity of modern integrated circuits. Hence, we propose GENESIS, a high-performance framework that extracts logic gates from GDSII with 100% accuracy with the fastest runtime. The proposed methodology uses sophisticated and efficient logic gate identification techniques to reduce runtime significantly. The evaluation was done on the different circuits of the ISCAS-85, ITC-99, and CEP benchmark suites. The methodology is tested on Nangate 45 nm technology nodes. The result shows that it can extract gate-level netlists from physical layout with 100% with a minimum run time of 0.5 sec, and the average faster runtime is 14X greater than the state-of-the-art methodology.