Design of A 5-10 GHz Open-Loop Quadrature Clock Generator for High-Speed Wireline Systems

This paper presents the design of an open-loop 4-phase quadrature clock generator (QCG) for high-speed wireline applications. The proposed QCG comprises a duty cycle correction (DCC) circuit, a digitally controlled delay line (DCDL), and a quadrature error correction (QEC) circuit based on phase interpolators (PI). The DCDL is calibrated to generate clock signals with a coarse quadrature phase error. The open-loop QEC further reduces the phase error to less than 1°. Simulations demonstrate a phase error $\leq 0.3^{\circ}$ across $5-10 \text{GHz}$ with an integrated jitter of $60.3 \text{fs}_{\text{rms}}$ and a power consumption of 9.7 mW at $10-\text{GHz}$ operation.