Low-Power Neural Network Accelerator for Sleep Stage Classification Using Chin Electromyography

This paper presents a low-power neural network accelerator (NNA) for sleep stage classification via chin electromyography signals. The proposed design integrates a fully connected neural network (FNN) with near-memory computing and 8-bit fixed-point arithmetic for low-power, high-efficiency inference. Weights and biases are stored in on-chip registers to minimize external memory access, reducing latency and improving energy efficiency. The fully placed-and-routed design, implemented in GlobalFoundries 22 nm fully depleted silicon-on-insulator (GF 22FD-SOI) technology, achieves a postplacement area of $0.0209 \text{mm}^{2}$, dynamic power consumption of $339 \mu \mathrm{W}$, and real-time operation at 100 MHz. On the ISRUC-Sleep dataset, the proposed FNN delivers recall scores of 86.8% for the awake stage, 85.9% for the rapid eye movement (REM) stage, and 85.6% for the non-rapid eye movement (NREM) stage, making it well-suited for wearable, battery-powered sleep monitoring devices.