RAAP-CGRA: Placement for CGRAs with Restricted Routing Architectures

Coarse-grained reconfigurable arrays (CGRAs) are programmable hardware devices that are word-level configurable, and can be used to implement application-specific accelerators, particularly for applications that can benefit from spatial and pipeline parallelism. A considerable portion of a CGRA’s silicon area is dedicated to realizing programmability, and it is desirable to reduce this overhead, while retaining flexibility and application mappability. This work considers CAD techniques for CGRAs with reduced interconnect flexibility. Specifically, we introduce Routing-Architecture-Aware Placement for CGRAs, RAAP-CGRA, comprising CGRA placement schemes suitable for CGRAs with restricted routing architectures. At a high level, the proposed schemes penalize placements likely to be unroutable due to architectural routing constraints. Experiments on three constrained CGRA architectures show our approaches significantly improve the success rate of mapping compared to a simulated-annealing-based baseline. For one CGRA architecture with restricted routing, a baseline mapper had an 11% average success rate, while one of the proposed mappers achieved a 61% success rate.