Unlocking Energy-Efficient and High-Throughput Secure Data Communication in IoT with Memory-Centric Computing

Traditional encryption methods in MCU-based IoT devices rely on software libraries or dedicated hardware, which introduce area overhead and frequent data transfers between SRAM and the accelerator, limiting performance and energy efficiency. We propose a memory-centric approach that repurposes SRAM arrays within MCUs for encryption, decryption, and authentication. This eliminates unnecessary data movement and leverages SRAM’s inherent bit-level parallelism, turning it into an active vector processing unit. By utilizing physical address access and DMA management, our solution achieves high parallelism and energy efficiency with minimal hardware overhead. Our method delivers up to 74× and 67× throughput improvements over software implementations for AES and SHA3, respectively, and up to 6× higher throughput compared to existing MCU hardware accelerators for AES. It also enables secure communication during low-power sleep modes.