Design and Implementation of a Low Power 4:2 Compressor Cell Using VTM-Logic Gates

This paper presents a design of a low-power 4:2 compressor cell design using Voltage-to-Memristance (VTM) logic gates. The authors have previously presented the VTM architecture for the efficient implementation of memory-based digital circuits, which includes the implementation of all basic logic gates. The novelty of the proposed circuit is using VTM-based memristor logic gates, which rely on achieving reduced hardware complexity and power consumption compared to previous designs. The proposed circuit was implemented through SPICE netlists in Cadence Virtuoso. Cadence Spectre was also used for design simulation and power measurement. The simulation results confirm the property of the design.