Formally Verifying RISC-V Code for Securing IoT with an Emphasis on Exception Handling

RISC-V is an open standard instruction set architecture that is being leveraged to create high-performance, low-power chips that can be targeted to IoT markets. In these markets, cybersecurity is often an after thought, or considered to provide too much overhead. This paper discusses the early stages of a project where we are building formal method models that can be used to verify the absence of security vulnerabilities in RISC-V code, reducing the need for complex security monitoring tools. This paper outlines the steps used to build a formal model of a 32-bit RISC-V assembly language with robust exception handling developed using the ACL2 theorem prover. The model identifies and responds to runtime faults, ensuring safe execution. Formal verification in ACL2 ensures that instructions remain within set bounds, preventing unexpected interruptions under valid conditions. This work addresses the critical need for secure and trustworthy hardware solutions, particularly in security-sensitive applications across many IoT domains where processor stability and fault tolerance are essential.