A 71—86-GHz Receiver with 5-GHz if Signal Bandwidth for E-Band Broadband Communication in 65-NM CMOS

This paper presents a $71-86-\text{GHz}$ receiver (RX) with $5-\text{GHz}$ IF bandwidth (BW) in $65-\text{nm}$ CMOS, which can be applied to high-speed and large-capacity wireless communications. The proposed receiver integrates a low-noise amplifier (LNA), a down-conversion mixer, and a baseband (BB) circuit that utilizes a mutually-coupled inductive load for wideband IF. Measurements show the receiver achieves a maximum conversion gain (CG) of 28 dB and a minimum single-sideband noise figure ($\text{NF}_{\text {ssb }}$) of 6.5 dB at $77-\text{GHz}$. The measured error vector magnitude (EVM) is less than -34 dB for $0.6 ~\text{Gb} / \mathrm{s} 64-\text{QAM}$ signals. The receiver occupies a chip area of $1.45 \times 1.09 ~\text{mm}^{2}$ with power consumption of $\mathbf{1 2 3. 4 ~ m W}$.