A 16-Way 115-129 GHz High Power Amplifier with 20.9 dBm $\mathrm{P}_{\text{SAT }}$ and 17.6 dBm $\mathrm{P}_{1 \text{dB}}$ in 40 Nm Bulk CMOS

This paper presents a $115-129 \text{GHz}$ power amplifier (PA) with a record $P_{\text{SAT }}$ in $40-\text{nm}$ bulk CMOS. The PA is based on a 4-stage differential common-source with cross-coupled capacitive neutralization with optimum device sizing and stage scaling with a transmission-line based low-loss 8:1 power combiner. On-wafer measurement shows 21.3 dB peak $S_{21}$ and 14 GHz 3-dB bandwidth, with $20.9 \text{dBm} P_{\text{SAT }}, 17.6 \text{dBm} P_{1 \text{dB}}$ and 7.6% power-added efficiency at 125 GHz at 1.2 V supply. The chip size of the PA is $1.34 \text{mm}^{2}$ including pads, with $0.69 \text{mm}^{2}$ core area. To the best of authors' knowledge, the proposed PA shows the highest $P_{\text{SAT }}$ and $P_{1 \text{dB}}$ for a $D$-band PA in CMOS.