MOSFET Compact Model Recalibration Based on Product-Related Layouts Using Bayesian Optimization

There is often a discrepancy between chip level hardware performance and the predictions from SPICE simulation using MOSFET compact models. With the scaling of advanced semiconductor technology, the complexity of device structures, physics, and models increases dramatically. Matching circuit level hardware measurements demands accuracy from SPICE simulations. In this work, we propose a new approach that drives compact model recalibration by matching product circuit targets to minimize the gap between chip level product performance and SPICE model prediction. In addition, our approach integrates accurate PEX netlists into the SPICE simulation used for model recalibration. PEX netlist-based model simulation becomes extremely time consuming for large circuits. To improve the overall efficiency, we utilize a parallel Bayesian optimization algorithm and associated software infrastructure to solve this multi-circuit optimization. Our experiments show a massive turn-around-time reduction from weeks to a few days for equal or better model quality as measured by predictions of circuit level metrics.