Recent Enhancements in the Industry-Standard Surface Potential-Based BSIM-SOI Compact Model

In this work, we present the recent advancements in the industry-standard surface potential-based BSIM-SOI compact model, designed for state-of-the-art SOI devices. The model incorporates a surface potential-based core that helps in the accurate modeling of partially depleted (PD), fully depleted (FD), and dynamically depleted (DD) regions, maintaining the inherent symmetry of the device. Enabled by a robust surface potential coupling relation, the model is well-suited for system-on-chip (SoC) designs, covering analog, digital, and RF applications. Key improvements include an updated effective mobility model, independent body resistances for the primary FET and process-induced parasitic opposite-type-gate FETs, decoupling of core I-V and C-V models, and integration of low-frequency shot noise for floating-body structures. These enhancements significantly improve the model's accuracy in capturing real hardware data. Additionally, proposed speed optimizations enhance the model's efficiency, making it more suitable for high-performance simulations.