Verification of Computational Memory Chip for Hidden Danger Identification of Transmission Lines Based on FPGA

The safe and stable operation of transmission lines is an important guarantee for the safety of large power grids. Through image monitoring and intelligent recognition, potential hazards such as construction machinery, foreign objects in conductors, and mountain fires within the transmission channels can be quickly detected, ensuring the safety of the lines. At present, the identification of a large number of potential hazards of transmission lines is completed in the cloud. In order to improve the timeliness of monitoring and reduce the operating power consumption of monitoring devices, there is an urgent need to achieve intelligent identification of potential hazards under lowpower consumption conditions within the devices. This paper focuses on the feasibility verification requirements of the on-site application of in-memory computing chips in transmission lines, and uses the FPGA prototype verification method to study and verify the non-von Neumann architecture cores. Build a verification platform combining FPGA and ARM, and realize the target detection based on the YOLOv3-tiny convolutional neural network through heterogeneous parallelism. By adopting optimization methods such as ping-pong buffering, layer fusion, and multi-channel data transmission, the performance of the accelerator is further enhanced, and the problems of limited hardware resources and data scheduling and circulation are solved. The performance of the FPGA chip core was verified through actual detection tasks. The total power consumption of the accelerator operation was 3.18 W, which met the on-site application conditions for transmission line monitoring.