Fast and Effective Logic Gate Sizing Based on Heterogeneous Graph Neural Network

Gate sizing serves as a fundamental netlist optimization technique for enhancing performance and power in the physical design flow. Traditional heuristic sizing algorithms prove computationally expensive, while existing machine learning approaches do not fully capture the influence of neighboring instances. In this work, we present a fast and effective end-to-end algorithm for post-placement logic gate sizing. It combines recursive feature elimination, a heterogeneous graph neural network encoder, and function-specific prediction heads to capture multi-scale graph information and learn high-quality instance representations, delivering accurate sizing solutions. Experimental results on ICCAD 2024 Contest benchmarks demonstrate that our method eliminates 98.6% of negative slacks, along with 99.2% of slew and load violations, achieving 12.86x acceleration over median contestant runtime. In terms of the contest evaluation metric, which balances performance gains, power savings, and computational efficiency, our approach secured third place in the contest.