DFTS: An Efficient Design-for-Test Flow for Scan Design

Modern integrated circuit (IC) development faces increasing demands for test coverage, cost efficiency, and reduced turnaround time, particularly with the shift to nanometer technology nodes and heterogeneous 3D integration. To address these challenges, we propose DFTS, a holistic Design-for-Test (DFT) methodology for scan design, consisting of five key components: netlist parsing, module uniquify operations, minimal MUX-based repairs of design rule checking (DRC) violations, balanced scan-chain construction, and clean circuit dumping for automatic test pattern generation (ATPG) or fault simulation. DFTS employs hierarchical parsing to capture clock, set, and reset domains accurately while minimizing redundant module definitions through unique operations. A selective DRC-violation repair mechanism efficiently inserts MUXes only where necessary, avoiding over-fixing in constant-gated or properly configured paths. Additionally, a multi-domain scan-chain balancing algorithm evenly distributes scan cells across clock domains, sharing switching activities across several clock domains and reducing the number of shift cycles. Experiments on CPU-like netlists demonstrated significant reductions in unnecessary MUX insertions and a runtime speedup of 3 –43 compared to a leading commercial DFT solution. Thes×e res×ults highlight the scalability and competitiveness of the proposed methodology, making it a robust solution for addressing DFT challenges in the scan design of modern ICs.