Stackable Thermal Model for 3D Integration

Vertical interconnects (VI) such as through silicon vias (TSVs), micro-solder bumps (µbumps), and controlled collapse chip connection (C4) bumps are critical for accurate thermal modeling in 3D IC. However, it has a high complexity to model such VI in thermal simulation. Therefore, it is necessary to develop efficient macromodels for early-stage planning, physical design, and quick verification. This paper develops an efficient yet accurate thermal model for 3D integration. We first map layers, which contain TSVs, µbumps and/or C4 bumps, to effective layers with homogeneous effective thermal conductivity. Moreover, we build a lookup table (LUT) of this conductivity for each type of effective layer separately, and show that these effective layers can be stacked to compute temperatures in 3D integration. Since effective layers with homogeneous conductivity can use sparse grids, temperature calculation using field solvers such as COMSOL is accelerated significantly. The experimental results show that our proposed macromodels achieve 60× speedup compared to the golden model simulated with COMSOL (from 30 minutes by COMSOL down to 30 seconds by our model). Furthermore, existing macromodel studies exhibit up to 5.71% error, whereas our model only has an error of 0.85% for maximum, minimum and mean temperatures. To the best of our knowledge, this paper is the first in-depth study on the layer-wise thermal macromodel for 3D integration with consideration of inter-die layers.