Low Mismatch Charge Pump Structure with Triple Feedback and Triple Bias

In the design of charge pump phase-locked loop (CP-PLL) systems, inherent CMOS device characteristics give rise to nonideal effects namely current mismatch, charge sharing, and clock feed through within the charge-pump architecture, which critically degrade loop performance. This paper proposes an improved low mismatch charge-pump topology. A triple bias dual feedback mechanism is combined with a bootstrap differential-switch technique to enhance current matching accuracy. In the first stage, a source-gate-connected current mirror generates the reference current. In the second stage, a high gain operational amplifier implements a dynamic negative feedback network to stabilize the PMOS and NMOS branch currents. And in the third stage, complementary switches and an op amp loop continuously adjust the operating point of the main current-source branch. These three parallel subsystems form a closed loop regulation mechanism. Experimental results indicate that, under a 1.8 V supply, the proposed structure achieves a charge or discharge current mismatch ratio of less than 0.1%, representing an order of magnitude improvement over conventional designs.