Enhanced BIST Architecture for Analog and Mixed-Signal Systems with On-Chip APRMLS and Machine Learning Analysis

This paper presents a Built-In Self-Test (BIST) architecture designed for linear and non-linear analog and mixedsignal systems. The proposed methodology combines on-chip generation of Amplitude-Modulated Pseudo-Random Multi Level Sequences (APRMLS) with a Machine Learning (ML) model for test response analysis. The APRMLS generator delivers precise and uniform excitation across the dynamic range of linear and non-linear systems, while the ML-based analyzer enhances fault detection accuracy and reliability. By automating the generation of optimized test stimuli and model parameters, the approach reduces external dependencies and lowers test costs. The ML model further enhances response analysis, delivering scalable and high-precision testing. This architecture establishes a promising framework for cost-effective, portable, and reliable testing of analog and mixed-signal systems.