A Photonic Interconnect Enabling Cross-Layer Scheduling for Chiplet-Based DNN Accelerators

Deep neural networks (DNNs) demand high-performance and energy-efficient hardware acceleration. Chiplet-based DNN accelerators offer a promising solution for scaling up DNN acceleration by integrating multiple chiplets. However, efficient interconnection of these chiplets remains a significant challenge. Traditional metallic interconnect suffers from limitations in both bandwidth and energy efficiency. Photonic interconnect, offering ultra-high bandwidth and energy efficiency, is emerging as a new interconnection technology for chiplet-based DNN accelerators. However, existing photonic interconnect designs lack the flexibility to implement advanced cross-layer scheduling, a crucial approach for enhancing computational efficiency in contemporary chiplet-based accelerators. To address this issue, we propose PICS, an efficient Photonic Interconnect design enabling flexible Cross-layer Scheduling for chiplet-based DNN accelerators. PICS incorporates a novel photonic interconnect architecture that facilitates efficient data transmission and flexible scheduling alongside a customized fine-grained scheduling and mapping framework. Compared to the state-of-the-art accelerator employing exclusively metallic interconnects with the state-of-the-art cross-layer scheduling framework, PICS demonstrates an average reduction of 9.5% and 31.9% in latency and energy consumption. Compared to the state-of-the-art accelerator employing photonic interconnects with the layer-sequential scheduling framework, PICS achieves an average reduction of 47.2% and 26.0% in latency and energy consumption.