Energy-Efficient Stochastic Spiking Neural Network Hardware with 8T SRAM Array Utilizing Sub-Threshold Cascaded Current Mirrors and Stochastic CMOS Leaky Integrate-and-Fire Neurons

Brain-inspired computing mechanisms are characterized by two primary features: 1) Sparse event-driven processing with spatio-temporal dynamics which result in low power consumption, and 2) Stochastic phenomena occurring between pre- and post-synaptic neurons, enhancing the stability and robustness of data processing.

This paper introduces an 8T SRAM-based Compute-In-Memory (CIM) architecture that capitalizes on these two key principles of brain-inspired computing. 1) By exploiting the inherent sparsity of spiking activity in SNNs, the architecture significantly improves energy efficiency in typical SNN applications by employing a cascaded current mirror that operates in sub-threshold region and dynamic latch-based Stochastic Leaky Integrate-and-Fire (LIF) neuron. 2) The noise characteristics inherent to CMOS comparators are effectively leveraged to implement stochastic activations within the SNN computations. Furthermore, the benefits of stochastic computing in enhancing the fault tolerance of neural networks, along with the associated trade-offs, are discussed. Fabricated using a 180nm CMOS process, the proposed SNN hardware exhibits high energy efficiency, achieving 0.1 pJ per synaptic operation (SOP). The SNN chip has been fully validated through on-chip classification tasks using the complete 10,000-sample MNIST test dataset. With 16 × 16 downsampled input images, the chip achieves an on-chip classification accuracy of 86.26%.