Design and Comparative Analysis of Ring Oscillator Using 250nm TSMC, and PTM Model

This paper presents the design and comparative analysis of 9-stage ring oscillator implemented using 250nm CMOS, real TSMC model and Predictive Technology Model (PTM). The oscillator's performance was evaluated across ${W_P}/{W_n}$ ratios (1 to 2.63) for oscillation frequency, propagation delay, average power consumption, and leakage current. Each model was simulated under identical design conditions using Tanner Tools EDA, to ensure a fair comparison. Results show PTM achieves up to 3.9% higher frequency and 5.3% lower delay but consumes 4.1% more power than TSMC. These findings guide designers in optimizing ring oscillators for high-speed or low-power applications.