Vertical Channel Transistor-Based OS-Si Hybrid Gain Cell for High-Density and High-Retention Embedded DRAM

This work proposes a 2T hybrid gain cell (HGC) architecture leveraging a vertical channel transistor (VCT) with oxide semiconductor (OS) channel material as BEOL access device, optimized for the 2 nm technology node. The integration of the VCT enables a compact 3D cell structure, yielding a 20% improvement in cell area efficiency, 74.2% reduction in write speed, and 242% increase in data retention compared to conventional TFT-based HGCs. By adjusting the VCT channel length, a tunable trade-off between access time and retention performance can be achieved, allowing for application-specific optimization. These advancements underscore the potential of VCT-based HGCs as a scalable, high-performance embedded DRAM solution for advanced logic nodes.