BloomTree: A High-Throughput and Easily Scalable Packet Classifier on FPGA for Large-Scale Rulesets With Fast Online Rule Updates

Packet classification plays a crucial role in computer networking such as quality of service and routing. With the continuous development of the internet, the scale of rule sets in packet classification continues to rapidly expand, leading to significant resource challenges for FPGA-based classification schemes. To this end, we propose an algorithm/hardware codesign scheme named BloomTree, which leverages off-chip DDR to store large-scale rule sets and conserve memory resources on FPGAs. To alleviate the memory access latency caused by the introduction of off-chip DDR, we innovatively combined the decision tree algorithm with the Bloom filter to prune invalid DDR accesses. The FPGA implementation of the proposed BloomTree adopts a fully pipelined architecture and possesses a dynamic update mechanism for pipelines, enabling both fast packet classification and flexible online rule update. The experimental results show that the proposed hardware architecture achieves average classification throughputs of 452.9 and 420.4 MPPS for the 10k rule sets and 140.9 and 71.8 MPPS for the 100k rule sets in the IPv4 and IPv6 scenarios, respectively. In addition, the update throughput can reach 71.4 MUPS. Compared with other methods that support dynamic rule updating, the proposed BloomTree utilizes the least memory resources on FPGAs and achieves $8.6\times $ to $64.7\times $ improvements in the speed to memory ratio.