A Behavioral Model for High-Speed 4:1 Analog Multiplexers, utilizing Stochastic Modelfitting

High-Speed DAC are essential components in optical transmitters for global communication networks. As the demand for increased analog bandwidth grows, the commonly used CMOS technology is approaching its limitations. A promising solution is the interleaving of multiple DAC outputs with an analog multiplexer (AMUX) implemented in silicon-germanium technology. In this work, a behavioral model for 4:1 AMUX ICs is presented, which reduces run times for system-level simulations by several orders of magnitude compared to post-layout IC simulations. The model was fitted using reference data from a 4:1 AMUX layout simulation, employing a stochastic algorithm to autonomously explore the parameter space. This approach demonstrates both faster computation and improved results compared to a brute force algorithm. The results indicate a close match of the reference and the model output, with low overfitting tendency.